VLSI IMP Questions

VLSI IMP Q's:

1.        Describe three sources of wiring capacitance, explain the effect of wiring capacitance on the performance of a VLSI circuit?

2.    (a) Explain the gate level and functional level of testing.

             (b) In a sequential circuit with ‘N’ i/ps and ‘M’ storage devices to test this circuit how many test  vectors are required?

             (c) What is sequential fault grading? Explain how it is analyzed?

        3. Draw the typical standard cell structure showing regular power-cell and explain it 

       4. Draw and explain the pseudo – nMOS PLA schematic for full adder and what are the advantages          and disadvantages of it.

          5. (a) what are the basic design units of VHDL? Explain them with suitable examples

          (b) compare the circuit level and logic level simulations for CMOS circuit
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